1. Field of the Invention
The present invention relates to an internal clock generation circuit, and particularly, to a voltage controlled oscillation circuit, used in a phase locked (synchronization) circuit, and having an oscillation frequency adjusted by a bias voltage.
2. Description of the Background Art
In data communication or the like, in order to reproduce transferred data correctly, a necessity arises for recovery of a clock signal in synchronization with a clock signal used in data transmission (a reference clock signal) and then, restoration of the data according to the recovered clock signal. In order to recover a clock signal that exactly tracks in frequency such a reference clock signal, there is generally used a phase locked circuit such as a PLL (a phase locked loop) or DLL (a delayed locked loop).
FIG. 31 is a diagram schematically showing a configuration of a conventional PLL circuit. In FIG. 31, the conventional phase locked circuit (PLL circuit) includes: a voltage controlled oscillation circuit (VCO) 900 having an oscillation frequency controlled by a control voltage VC to generate a recovered dock signal RCLK; a phase comparison circuit 904 comparing in phase recovered clock signal RCLK outputted by voltage controlled oscillation circuit 900 and a reference clock signal CLK with each other to generate a signal corresponding to a phase difference; and a charge pump 906 performing a charge/discharge operation according to a phase difference indicating signal from phase comparison circuit 904 to generate control voltage VC and apply control voltage VC to voltage controlled oscillation circuit 900. Charge pump 906 includes a loop filter to remove a high frequency component of an output thereof and generate control voltage VC.
In the PLL circuit shown in FIG. 31, a negative feedback closed loop is constituted of voltage controlled oscillation circuit 900, phase comparison circuit 904 and charge pump 906, and control voltage VC is adjusted by phase comparison circuit 904 such that a phase difference becomes 0 (zero) between recovered clock signal RCLK and reference clock signal CLK and accordingly the oscillation frequency of voltage controlled oscillation circuit 900 is adjusted. By utilization of a negative feedback of the closed loop, correct frequency tracking can be performed on reference clock signal CLK to generate recovered clock signal RCLK.
FIG. 32 is a diagram showing an example of a configuration of voltage controlled oscillation circuit 900 shown in FIG. 31. Voltage controlled oscillation circuit 900 shown in FIG. 32 is a ring oscillator type voltage controlled oscillation circuit.
In FIG. 32, voltage controlled oscillation circuit 900 includes: a bias voltage generation circuit 900a for generating bias voltages VC1 and VC2 according to control voltage VC; and an oscillation circuit 900b having an oscillation frequency controlled by bias voltages VC1 and VC2. Oscillation circuit 900b includes delay circuits D1 to Dn cascaded in plural stages. An output signal OUT (recovered clock signal RCLK) is generated from delay circuit Dn at the final stage. The output signal of delay circuit Dn at the final stage is fed back to delay circuit D1 at the first stage. Delay circuits D1 to Dn are connected in a ring shape to constitute a ring oscillator.
Bias voltage generation circuit 900a includes: a P channel MOS transistor M2 connected between a power supply node and an internal node AN, and having a gate connected to internal node AN; an N channel MOS transistor (insulated gate field effect transistor) M1 connected between node AN and a ground node, and receiving control voltage VC at the gate thereof, a P channel MOS transistor M3 connected between the power supply node and an internal node BN, and having a gate connected to internal node AN; and an N channel MOS transistor M4 connected between internal node BN and the ground node, and having a gate connected to internal node BN. MOS transistors M2 and M3 constitutes a current mirror circuit, wherein MOS transistor M2 serves as a master transistor, while MOS transistor M3 serves as a slave transistor. Bias voltage VC1 is generated at the gates of MOS transistors M2 and M3. MOS transistor M4 has the gate and drain connected to each other and has the gate voltage set according to the drain current thereof. That is, the gate and drain voltages of MOS transistor M4 are determined such that a discharge current of MOS transistor M4 and a supply current of MOS transistor M3 are in balance with each other. Bias voltage VC2 is generated at the gate and drain of MOS transistor M4.
In oscillation circuit 900b, each of delay circuits D1 to Dn is of the same configuration as is the others and therefore, reference numerals are attached to components of delay circuit Dn at the final stage as a representative. Delay circuit Dn includes: P channel MOS transistors MC1 and MC5 connected in series between a power supply node and an internal output node; and N channel MOS transistors M6 and MC2 connected in series between the internal output node and a ground node. Bias voltages VC1 and VC2 are applied to the gates of respective MOS transistors MC1 and MC2. An output signal of delay circuit (D(n-1)) at the stage previous to the final stage is applied to the gates of MOS transistors M5 and M6 at the final stage.
By applying bias voltages VC1 and VC2 to MOS transistors MC1 and MC2, drive current amounts of MOS transistors MC1 and MC2 are set. MOS transistors MC1 and M2 constitute a current mirror circuit and MOS transistors MC2 and M4 constitute another current mirror circuit. In a case where each of the MOS transistors M3, M4, MC1 and MC2 has the same transistor size as others, currents of the same magnitude flow through the respective MOS transistors M3, M4, MC1 and MC2.
When a voltage level of control voltage VC rises, a conductance of MOS transistor M1 increases to increase a current amount flowing to the ground from MOS transistor M2 through MOS transistor M1. A mirror current of a current supplied by MOS transistor M2 is generated by MOS transistor M3 and supplied to MOS transistor M4. A voltage level of internal node AN is the level at which a current amount that MOS transistor M2 supplies and a current amount that MOS transistor M1 discharges are in balance with each other. Likewise, a voltage of internal node BN is the level at which a current amount that MOS transistor M3 supplies and a current amount that MOS transistor M4 discharges are in balance with each other.
Therefore, when control voltage VC rises, a voltage level of node AN lowers and a voltage level of bias voltage VC1 drops, while a voltage level of node BN rises and bias voltage VC2 rises. With such bias voltage levels, in each of delay circuits D1 to Dn of oscillation circuit 900b, a drive current amount of MOS transistor MC1 increases and a drive current of MOS transistor MC2 increases. Therefore, operating currents of delay circuits D1 to Dn increases to cause operating speeds of delay circuits D1 to Dn to be faster and increase an oscillation frequency of oscillation circuit 900b. 
On the other hand, when control voltage VC lowers, a conductance of MOS transistor M1 decreases to decrease a drive current amount thereof. In response, a supply current of MOS transistor M2 decreases to raise a voltage level of internal node AN. With increase of the voltage level at internal node AN, a voltage level of bias voltage VC1 rises and drive current amounts of MOS transistors MC2 and MC4 is reduced and therefore, a voltage level of bias voltage VC2 lowers.
Accordingly, operating current amounts of delay circuits D1 to Dn of oscillation circuit 900b decrease, a delay time is longer; therefore, oscillation frequency of oscillation circuit 900b decreases.
Control voltage VC is at a voltage level corresponding to a phase difference between recovered clock signal RCLK and reference clock signal CLK, and by adjusting the operating current amount of oscillation circuit 900b so as to cause the phase difference to be 0 (zero), an oscillation frequency of oscillation circuit 900b is adjusted to cause a frequency of recovered clock signal RCLK to track that of reference dock signal CLK and thus, a phase of recovered clock signal RCLK is locked at that of reference clock signal CLK.
Currents of the same magnitude flow in MOS transistors M3 and M4 of bias voltage generation circuit 900a (in equilibrium). In oscillation circuit 900b, current source transistors MC1 and MC2 constitute current mirror circuits with respective MOS transistors M2 and M4, and therefore, drive current amounts of current source transistors MC1 and MC2 are equal to each other at all times and thereby, in each of delay circuit D1 to Dn, a rise time and fall time of an output signal are both controlled according to control voltage VC.
FIG. 33 is a graph showing a relationship between control voltage VC and oscillation signal FB of voltage controlled oscillation circuit 900. As shown in FIG. 33, when a voltage level of control voltage VC rises, oscillation frequency FB increases. Herein, a frequency range in which a phase locked loop (a negative feedback closed loop) operates is simply referred to as xe2x80x9ca frequency rangexe2x80x9d, and a voltage range in which a phase locked loop operates stably is simply referred to as xe2x80x9ca voltage rangexe2x80x9d. In order to stably operate a phase locked loop at all times, it is preferable to set the frequency range and the voltage range as wide as possible. With extension of frequency range and voltage range, a recovered dock signal correctly tracking a reference clock signal in frequency can be stably generated over a wider operating frequency range.
As shown in the graph of FIG. 33, in order to extend a frequency range, a necessity arises for extension in voltage range of control voltage VC. The lower limit of control voltage VC, however, is determined by a threshold voltage Vth of MOS transistor M1 of bias voltage generation circuit 900a. When control voltage VC becomes lower than the threshold voltage of MOS transistor M1, MOS transistor M1 enters a nonconductive state to disable bias voltage generation circuit 900a to generate a bias voltage. On the other hand, a power supply voltage of a reduced voltage level is employed for low power consumption and high speed operation, and therefore, a voltage range of control voltage VC is limited in range from the threshold voltage of MOS transistor M1 to a power supply voltage level, thereby, disabling a sufficiently wide voltage range to be ensured under the condition of a low power supply voltage.
In the above configuration of an internal clock generation circuit, current source transistors MC1 and MC2 are provided in the high level power supply side and the low level power supply side, respectively, in each of delay stages D1 to Dn and drive currents of current source transistors MC1 and MC2 are controlled according to bias voltages VC1 and VC2. In each of the delay stages, however, a current source transistor may be provided only in one of the high level power supply side and low level power supply side.
In such a configuration of the delay stages, no current mirror circuit is necessary in a bias voltage generation circuit and a bias voltage is generated merely by a current/voltage conversion element corresponding to a master transistor M2 according to a drive current of an input transistor. In such an internal clock generation circuit as well, since an operating current in each delay stage is controlled by control voltage VC, there arises a problem similar to that of the internal dock generation circuit shown in FIG. 32.
It is an object of the present invention to provide an internal clock generation circuit capable of ensuring a sufficiently wide operating range (voltage range) under the condition of a low power supply voltage.
It is another object of the present invention to provide a voltage controlled oscillation circuit capable of stably operating a phase locked loop even under the condition of a low power supply voltage.
An internal dock generation circuit according to a first aspect of the present invention includes: a bias voltage generation circuit including an insulated gate field effect input transistor receiving a control voltage at a gate thereof, and generating a bias voltage according to the control voltage. The insulated gate field effect input transistor receives a voltage having a voltage level different from a voltage of a power supply node at a back gate thereof.
The internal clock generation circuit according to the first aspect of the present invention further includes: a clock generation circuit including a plurality of cascaded delay circuits having respective operating currents determined according to the bias voltage.
An internal clock generation circuit according to a second aspect of the present invention includes: an bias voltage generation circuit generating a bias voltage according to a control voltage; and a clock generation circuit including a plurality of cascaded delay circuits having respective operating currents determined by the bias voltage. Each of the delay circuits includes: a current source insulated gate field effect transistor, coupled to a power supply node, receiving a voltage at a voltage level different from a voltage of the power supply node at a back gate thereof and receiving the bias voltage at a gate thereof.
An internal clock generation circuit according to a third aspect of the present invention includes: a bias voltage generation circuit generating a bias voltage according to a control voltage. The bias voltage generation circuit includes: an input transistor receiving the control voltage at a gate thereof; and a current source circuit coupled between the input transistor and a power supply node, and having a drive current determined according to a conductance of the input transistor. The current source circuit includes: a current/voltage conversion element converting the drive current to a voltage to generate the bias voltage. The current/voltage conversion element includes: an insulated gate field effect transistor receiving a base voltage at a voltage level different from a voltage of the power supply node at a back gate thereof.
The internal clock generation circuit according to the third aspect of the present invention further includes: a clock generation circuit including a plurality of cascaded delay circuits having respective operating currents determined by the bias voltage. Each of the delay circuits includes a current source transistor having a drive current determined by the bias voltage from the bias voltage generation circuit. The current source transistor includes an insulated gate field effect transistor having a backgate connected to a backgate of an insulated gate field effect transistor of the current/voltage conversion element.
An internal clock generation circuit according to a fourth aspect of the present invention includes: a bias voltage generation circuit generating a bias voltage according to a control voltage. The bias voltage generation circuit includes: an input element having a conductance changing according to the control voltage; a current mirror current source circuit having a drive current determined according to the conductance of the input element; and an output transistor having a drive current determined by the drive current of the current source circuit. The current source circuit includes: an insulated gate field effect master transistor coupled between the input element and a first power supply node, and having a drive current determined by a conductance of the input transistor and generating a first bias voltage; and an insulated gate field effect slave transistor having a drive current determined by the drive current of the master transistor. The master and slave transistors receive a voltage at a voltage level different from a voltage of the first power supply node at their respective backgates, and the output transistor is coupled between the slave transistor and a second power supply node and receives a voltage at a voltage level different from a voltage of the second power supply node and generates a second bias voltage according to the drive current of the slave transistor.
The internal clock generation circuit according to the fourth aspect of the present invention further includes: a clock generation circuit including a plurality of cascaded delay circuits having respective operating currents determined according to the first and second bias voltage. Each of the delay circuits includes: a first current source transistor constituted of an insulated gate field effect transistor of a first conductivity type receiving the first bias voltage at a gate thereof, and having a backgate connected to backgates of the master and slave transistors; and a second current source transistor constituted of an insulated gate field effect transistor of a second conductivity type receiving the second bias voltage at a gate thereof, and having a backgate connected to the backgate of the output transistor.
By controlling a backgate voltage of an insulated gate field effect transistor, a backgate bias effect (a substrate effect) is caused to serve and thereby, the absolute value of a threshold voltage of the insulated gate field effect transistor can be decreased to extend a voltage range of the control voltage. Furthermore, with extension in voltage range of the control voltage, a voltage range of the clock generation circuit can be extended, thereby, enabling a wide voltage range to be ensured even under the condition of a low power supply voltage.
Furthermore, by changing a backgate voltage of an insulated gate field effect transistor according to the control voltage, a threshold voltage thereof can be changed according to a value of the control voltage, thereby enabling a linearity in response of a bias voltage to the control voltage to be improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.